The present invention relates to integrated circuitry that can perform operations in parallel.
Hillis et al., U.S. Pat. No. 4,709,327, describe a parallel processor/memory circuit for use in a highly parallel processor. As shown and described in relation to FIGS. 1A and 5 of the patent, an array of parallel processing integrated circuits (ICs) contains 32,768 identical ICs, each containing 32 identical processor/memories. For rapid interchange of data in random directions between processor/memories, the ICs are interconnected in a Boolean n-cube of fifteen dimensions. Each IC includes logic circuitry to control routing of messages within the interconnection network, shown and described in detail in relation to FIGS. 6B and 11-16, and includes bus connections from the routing circuitry to its processor/memories so that every processor/memory in the array can send a message to every other processor/memory. As shown and described in relation to FIGS. 6A and 17, the processor/memories on an IC are connected in an array but are laid out in groups of four with bus drivers interspersed between them. Each processor/memory includes 384 bits of dynamic read-write storage (RAM), addressing circuitry, an ALU, a flag register, addressing circuitry for the flag register, and various driver circuits, shown and described in detail in relation to FIGS. 7A and 7B. As shown and described in relation to FIG. 6B, each IC also includes a programmable logic array (PLA) that receives and decodes instructions that are then used by the processor/memories. As shown and described in relation to FIG. 17, a signal bus from the PLA to the processor/memories is an array of lines, and the signal flow in the processor/memory is essentially at right angles to the bus to minimize line crossings and simplify circuit layout. Approximately 1800 transistors are required to implement one processor/memory in VLSI. As shown and described in relation to FIGS. 7A and 7B, the ALU of a processor/memory operates on data from two registers in RAM and one flag input, and produces a sum output that is written into one of the RAM registers and a carry output that is available to registers in the flag controller and to certain other processor/memories. ALU operations take place in two cycles, a read cycle and a conditional write cycle. The RAM includes twelve registers of thirty-two bits each, with each bit separately addressable by column. Register address lines are provided to access up to 16 registers. The ALU includes a one-out-of-eight decoder, a sum output selecter, and a carry output selector. The ALU can produce the sum and carry outputs of thirty-two functions that are all variations of the five basic operations ADD, OR, AND, MOVE, and SWAP.
Mick, J., and Brick, J., Bit-slice Microprocessor Design, McGraw-Hill, 1980, pp. 93-127 describe the Am2901A and Am2093, arithmetic logic unit/function generators that perform arithmetic/logic operations on two four-bit input variables. FIG. 7 shows a simple data handling path of a minicomputer. FIG. 13 shows the Am2901A architecture, with more detail in FIG. 14. All data paths within the circuit are four bits wide. Data can be read from any two of the words in the 16-word by 4-bit 2-port RAM and provided to the ALU and the result written to the location of one of the two words. The ALU, a high-speed arithmetic/logic operator, can perform three binary arithmetic and five logic operations on the two 4-bit input words, as shown in FIG. 15. FIG. 16 shows the Am2903 architecture, which performs all the functions of the Am2901A and has enhancements enabling it to perform special functions as shown in FIG. 17 and seven arithmetic and nine logic operations on two 4-bit operands, as shown in FIG. 18.
Toshiba MOS Memory Products Data Book, February 1989, pp. B-57 through B-102, describes TC524257P/Z/J-10 and -12 CMO multiport memory with a 262,144-word.times.4 bit dynamic random access memory (RAM) port and a 512-word.times.4 bit static serial access memory (SAM) port. As explained at page B-57, these products feature a logic function and a write-per-bit function on the RAM port. Page B-58 shows a block diagram of the products, including memory array, row decoder, column decoder, I/O gate, sense amp, transfer gate, serial register, serial selector, logic operation, and write-per-bit control. FIGS. 2 and 3 and Table 2 on page B-68 illustrate a write-per-bit function that selectively controls the internal write-enable circuits of the RAM port for application to displays. FIGS. 4-6 and Table 3 on pages B-69 through B-71 illustrate a logic function that provides 16 modes of raster operation. As shown in FIG. 4, a logical operation is performed on input data and data in a destination cell and the result is then stored in the destination cell.